Commits · master · sdiy / clockgen · GitLab

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Nov 08, 2018
- updated bom/csv · 94bd6bcc
  tee authored Nov 8, 2018
  
  94bd6bcc
- added forgotten R7 · d69dbf05
  tee authored Nov 8, 2018
  
  d69dbf05
- Update README.md · b1e228ef
  Tee authored Nov 8, 2018
  
  b1e228ef
- updated powersection · d5ac6d3a
  tee authored Nov 8, 2018
  
  d5ac6d3a
- mirrored 1st opamp, added resistors for LED and inverted output · c4f79a4d
  tee authored Nov 8, 2018
  
  c4f79a4d
- added clockgen-sim.png · e62d348b
  tee authored Nov 8, 2018
  
  e62d348b
- added .gitignore · ad6f22d8
  tee authored Nov 8, 2018
  
  ad6f22d8
- Made simulation more beautiful : ) · a0743b43
  David Huss authored Nov 8, 2018
  
  a0743b43
- Added Simulation · e39b70ce
  David Huss authored Nov 8, 2018
  
  e39b70ce
- Added image and simulation · 617ab855
  David Huss authored Nov 8, 2018
  
  617ab855
- renamed README · 6cb1ed06
  t6 authored Nov 8, 2018
  
  6cb1ed06
- initial import · 59b1973a
  t6 authored Nov 8, 2018
  
  59b1973a