Commit e39b70ce authored by David Huss's avatar David Huss 💬

Added Simulation

parent 617ab855
......@@ -3,5 +3,6 @@ Simple bipolar clock generator with PWM, buffered outputs, one inverted output a
![Clockgen Schematic](clockgen-simple-ws2018.png)
Simulation [is here](http://tinyurl.com/ybsu7nqu)
v0.1 20181108
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