Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
C
clockgen
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
sdiy
clockgen
Commits
617ab855
Commit
617ab855
authored
6 years ago
by
David Huss
Browse files
Options
Downloads
Patches
Plain Diff
Added image and simulation
parent
6cb1ed06
Branches
Branches containing commit
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
README.md
+3
-0
3 additions, 0 deletions
README.md
with
3 additions
and
0 deletions
README.md
+
3
−
0
View file @
617ab855
# Clockgen
Simple bipolar clock generator with PWM, buffered outputs, one inverted output and two-colour-LED indicating the output signal.
v0.1 20181108
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment
