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sdiy
clockgen
Commits
Commits · d5ac6d3a6bacd81e038d7bd4e67d30981d137dcf
d5ac6d3a6bacd81e038d7bd4e67d30981d137dcf
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d5ac6d3a6bacd81e038d7bd4e67d30981d137dcf
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2 results
clockgen
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authors
Bernd Flickenschild
flischi
David Huss
dh
Konrad Krenzlin
konradkrenzlin
Tee
t6
felix r
felix
torben spieker
torben
6 authors
Browse files
Nov 08, 2018
updated powersection
· d5ac6d3a
tee
authored
Nov 8, 2018
d5ac6d3a
mirrored 1st opamp, added resistors for LED and inverted output
· c4f79a4d
tee
authored
Nov 8, 2018
c4f79a4d
added clockgen-sim.png
· e62d348b
tee
authored
Nov 8, 2018
e62d348b
added .gitignore
· ad6f22d8
tee
authored
Nov 8, 2018
ad6f22d8
Made simulation more beautiful : )
· a0743b43
David Huss
authored
Nov 8, 2018
a0743b43
Added Simulation
· e39b70ce
David Huss
authored
Nov 8, 2018
e39b70ce
Added image and simulation
· 617ab855
David Huss
authored
Nov 8, 2018
617ab855
renamed README
· 6cb1ed06
t6
authored
Nov 8, 2018
6cb1ed06
initial import
· 59b1973a
t6
authored
Nov 8, 2018
59b1973a
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tee authored
tee authored
tee authored
tee authored
David Huss authored
David Huss authored
David Huss authored
t6 authored
t6 authored