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sdiy
clockgen
Commits
94bd6bcceaae62badf876362f7ed2f9150b25cb4
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clockgen
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Nov 08, 2018
updated bom/csv
· 94bd6bcc
tee
authored
6 years ago
94bd6bcc
added forgotten R7
· d69dbf05
tee
authored
6 years ago
d69dbf05
Update README.md
· b1e228ef
Tee
authored
6 years ago
b1e228ef
updated powersection
· d5ac6d3a
tee
authored
6 years ago
d5ac6d3a
mirrored 1st opamp, added resistors for LED and inverted output
· c4f79a4d
tee
authored
6 years ago
c4f79a4d
added clockgen-sim.png
· e62d348b
tee
authored
6 years ago
e62d348b
added .gitignore
· ad6f22d8
tee
authored
6 years ago
ad6f22d8
Made simulation more beautiful : )
· a0743b43
David Huss
authored
6 years ago
a0743b43
Added Simulation
· e39b70ce
David Huss
authored
6 years ago
e39b70ce
Added image and simulation
· 617ab855
David Huss
authored
6 years ago
617ab855
renamed README
· 6cb1ed06
t6
authored
6 years ago
6cb1ed06
initial import
· 59b1973a
t6
authored
6 years ago
59b1973a
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tee authored
tee authored
David Huss authored
David Huss authored
David Huss authored
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t6 authored